1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Related Art
In recent semiconductor devices, delay in signal transmission on interconnects may sometimes determine operation speed of LSI circuits. Delay constant of signal transmission on interconnects is expressed by a product of interconnect resistance and parasitic capacitance. In order to reduce the parasitic capacitance, a low-dielectric-constant material (low-k material) having a dielectric constant smaller than that of the conventionally-used silicon dioxide (SiO2) has been used as a material for composing insulating interlayer. On the other hand, in view of reducing resistivity of the interconnects so as to raise operation speed of the LSI circuits, copper (Cu) having a small resistivity has been used as an electro-conductive material.
Cu multi-layered interconnect may be formed by the damascene process. The damascene process includes a step of depositing an insulating film such as an insulating interlayer, a step of forming recesses (interconnect trenches for forming interconnects, or via holes for forming via plugs), a step of depositing barrier metal layer, a step of depositing a Cu thin film called Cu seed, a step of filling the recesses by depositing Cu using the Cu thin film as a cathode of electrolytic plating, a step of removing a portion of the barrier metal layer formed outside the recesses by chemical mechanical polishing, and a step of depositing a barrier insulating film.
As for the insulating interlayer, porous low-dielectric-constant materials have been discussed aiming at reducing the dielectric constant to as small as 2 or around.
N. Ohashi, K. Misawa, S. Sone, H. J. Shin, K. Inukai, E. Soda, S. Kondo, A. Furuya, H. Okamura, S. Ogawa and N. Kobayashi, “Robust Porous MSQ (k=2.3, E=12 GPa) for Low-Temperature (<350° C.) Cu/Low-k Integration Using ArF Resist Mask Process”, Proceedings of IEEE International Electron Devices Meeting 2003, pp. 35.5.1-35.5.4. points out problems in the porous low-dielectric-constant materials, such as lowering in the material strength, elevation of dielectric constant caused by moistening, and corrosion of the porous dielectric materials called low-k void, and discloses a technique of solving these problems by optimizing composition of the low-dielectric-constant material, and etching method in the damascene process.
N. Matsunaga, N. Nakamura, K. Higashi, H. Yamaguchi, T. Watanabe, K. Akiyama, S. Nakao, K. Fujita, H. Miyajima, S. Omoto, A. Sakata, T. Katata, Y. Kagawa, H. Kawashima, Y. Enomoto, T. Hasegawa and H. Shibata, “BEOL Process Integration Technology for 45 nm Node Porous Low-k/Copper Interconnects”, Proceedings of the IEEE International Interconnect Technology Conference 2005, pp. 6-8 discloses a technique of providing a dummy pattern, aiming at preventing oxidation of the barrier metal layer due to gas released by the porous insulating interlayer.
Japanese Laid-Open Patent Publication No. 2005-236285 discloses a technique of depositing a high-density dielectric material between the porous low-dielectric-constant material and the barrier metal layer, in order to prevent the barrier metal layer from being thinned due to irregularities conforming to voids of the porous low-dielectric-constant material, and from being degraded in reliability.
On the other hand, as for the electro-conductive material, thinning of the Cu seed has been discussed, aiming at improving Cu filling. Because holes in Cu interconnects (called voids, referred to as “voids” hereinafter) are known to degrade electrical characteristics (resistance, reliability, yield ratio, etc.), void-less filling is of importance in Cu plating.
Rate of formation of film in the Cu plating is faster at around the frontage and the bottom of the recess. Therefore, the void-less filling may successfully be achieved if Cu plating grown from the bottom of the recess reaches the frontage of the recess, before the frontage of the recess is clogged by the Cu plating. It may therefore be understood that wider frontage can facilitate the void-less filling.
On the other hand, the Cu seed has been becoming more thinner with recent progress of shrinkage of devices, so that it has been discussed to directly plate Cu on the barrier metal using the barrier metal per se as a seed, rather than depositing the Cu seed.
In particular, ruthenium (Ru) showing a good adhesiveness with Cu has been attracting much public attention as a barrier metal. Because Ru retains the electro-conductivity even after being oxidized, it has been attracting much attention also from the viewpoint of widening process margin with respect to the filling by plating. Japanese Laid-Open Patent Publication No. 2002-75994 discloses a technique of using a barrier metal composed of a metal (Ru, etc.) showing electro-conductivity even after being oxidized, or an oxide thereof. Use of Ru as the barrier metal, however, suffers from a problem in adhesiveness, because the metal state of which shows only a poor adhesiveness to the insulating interlayer, and an oxide state of which shows only a poor adhesiveness to Cu. Efforts of improvements have been made typically as seen in Japanese Laid-Open Patent Publication Nos. 2000-269455, 2005-347510, 2006-5305, and 2006-19325.
Japanese Laid-Open Patent Publication No. 2000-269455 discloses a technique of using a barrier metal composed of a metal showing electro-conductivity even after being oxidized (Ru, etc.) or its oxide, added with Pd or the like.
Japanese Laid-Open Patent Publication No. 2005-347510 discloses a technique of using a barrier metal composed of a C, N or Si compound of a metal showing electro-conductivity even after being oxidized (Ru, etc.), a transition layer, and a metal showing electro-conductivity even after being oxidized, stacked in this order as viewed from the insulating film side.
Japanese Laid-Open Patent Publication No. 2006-5305 discloses a technique of using a barrier metal composed of an oxide of a metal showing electro-conductivity even after being oxidized (Ru, etc.), a transition layer, and a metal, stacked in this order as viewed from the insulating film.
Japanese Laid-Open Patent Publication No. 2006-19325 discloses a technique of raising elastic modulus of the transition layer, in order to improve a poor mechanical strength in the configuration shown in Japanese Laid-Open Patent Publication No. 2006-5305.
However, the present inventor found out, from his investigation, a problem in that use of the metal oxide film, as described in Japanese Laid-Open Patent Publication Nos. 2000-269455, 2005-347510, 2006-5305, and 2006-19325 may degrade the adhesiveness between the upper interconnect and the lower interconnect, and may consequently degrade electrical characteristics and reliability. This is because Cu contained in the lower interconnect is oxidized due to an oxidative atmosphere used for forming the metal oxide film.
A possible method of preventing oxidation of Cu contained in the lower interconnect in the process of forming the metal oxide film may be such as depositing a high-density dielectric film on the insulating interlayer, and then depositing the barrier metal, based on combination of the inventions described in Japanese Laid-Open Patent Publication Nos. 2005-236285, 2000-269455, 2005-347510, 2006-5305, and 2006-19325. Oxidation of Cu contained in the lower interconnect is, however, inevitable because the thickness of the high-density dielectric film at the bottom of the recess will be as small as several nanometers in the generation of a technical node of 45 nm or thereafter. Oxidation of Cu contained in the lower interconnect may raise problems of increase in resistivity of the interconnects, and degradation of the reliability.
Although the description in the above has been made assuming the cases where a via-forming layer is formed on an interconnect layer by the single damascene process, or where a via-and-interconnect-forming layer is formed by the dual damascene process, the same problem resides also for the case where an interconnect layer is formed on the via plug.